Shared Resource Contention in Real-Time Systems
Developing mitigation techniques for resource contention in real-time-systems.
Project: Providing Determinism and Performance through Bandwidth Regulation
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Background: Modern commercial-off-the-shelf (COTS) multicore processors feature advanced memory hierarchies that enhance memory-level parallelism (MLP), essential for high performance. However, uneven distribution of cache requests from multiple cores can lead to significant contention, affecting all cores and potentially being exploited through cache bank-aware denial-of-service (DoS) attacks to disrupt system timing predictability.
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Objective: Our project investigates the impact of cache bank contention in multicore processors and explores mitigation strategies to ensure consistent and predictable system performance. By analyzing the causes and effects of contention and developing solutions to minimize it, we aim to improve the robustness and security of multicore systems.
The design was implemented and evaluated on real hardware using an FPGA SoC Framework:
- Hardware: Beagle-V Ahead, Raspberry Pi 4
- Implementation Tools: FireSim, Chipyard SoC Framework
- Analysis Tools: Cadence Genus, Innovus, Voltus
- Benchmarks: Synthetic, SD-VBS, SPEC 2017
Related publications: (Sullivan et al., 2024)
